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6 bit 3 8 4 channel tft - lcd source driver august . 1999. ver. 0. 0 prepared by: myoung-sik, suh mail to: mssuh @samsung.co.kr ks0 672 contents in this document are subject to change without notice. no part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of lcd driver ic team.
ks 0672 6 bit 384 channel tft-lcd source driver 2 ks0 672 specification revision history version content date 0.0 original aug . 1999
6 bit 384 channel tft-lcd source driver KS0672 3 contents introduction ................................ ................................ ................................ ................................ ................. 4 features ................................ ................................ ................................ ................................ ......................... 4 block diagram ................................ ................................ ................................ ................................ .............. 5 pin assignments ................................ ................................ ................................ ................................ ............ 6 pin descriptions ................................ ................................ ................................ ................................ ........... 7 operation description ................................ ................................ ................................ ............................... 8 display data transfer ................................ ................................ ................................ ............................ 8 extension of output ................................ ................................ ................................ ............................... 8 relationship between input data value and output voltage ................................ .................. 8 absolute maximum ratings ................................ ................................ ................................ .................... 15 recommended operation conditions ................................ ................................ ................................ .. 15 dc characteristics ................................ ................................ ................................ ................................ ... 16 ac characteristics ................................ ................................ ................................ ................................ ... 17 waveforms ................................ ................................ ................................ ................................ ................... 18 relationships between clk1, start pulse (dio1, dio2) and blanking period ........................ 19
ks 0672 6 bit 384 channel tft-lcd source driver 4 introduction the KS0672 is a 384 channel output, tft - lcd source driver for 64 gray scale displays. data input is based on digital input consisting of 6 bits by 6 dots, which can realize a full-color display of 260,000 colors by output of 64 values gamma -corrected. this device has an internal d/a ( d igital-to- a nalog) converter for each output and 10 (5-by-2) external power supplies. because the output dynamic range is as large as 6 . 6 - 1 2 . 6 vp-p, it is unnecessary to operate level inversion of the lcd's common electrode. besides, to be able to deal with dot-line inversion when mounted on a single-side, output gray scale voltages with different polarity can be output to the odd number output pins and the even output pins. KS0672 can be adopted to larger panel, and shl ( s hift d irection s election) pin makes use of the lcd panel connection conveniently. maximum operation clock frequency is 65 mh z at a 2.7 v logic operation . i t can be applied to the tft - lcd panel of xga, sxga standards. features tft active matrix lcd source driver lsi 64 gray scale is possible through 10 (5 by 2) external power supply and d/a converter both dot inversion display and n - line inversion display are possible cmos level input compatible with gamma-correction input data inversion function (datpol) logic supply voltage: 2. 7 - 3.6 v lcd driver supply voltage: 7.0 - 1 3.0 v output dynamic range: 6 . 6 - 1 2 . 6 vp-p maximum operating frequency: fmax = 65 mhz (internal data transmission rate at 2.7 v operation) o utput: 384 outputs tcp
6 bit 384 channel tft-lcd source driver KS0672 5 block diagram output buffer d/a converter data register 64bit shift register data control shl 6 y001 y002 y003 y382 y383 y384 dio2 dio1 clk2 d00 - d05 d10 - d15 d20 - d25 d30 - d35 d40 - d45 d50 - d55 6 6 6 6 6 datpol 36 6 6 6 6 6 6 vgma1 - vgma10 10 data latch 6 6 6 6 6 6 bias pol clk1 test figure 1. KS0672 block diagram
ks 0672 6 bit 384 channel tft-lcd source driver 6 pin assignments y001 y002 y003 y004 y384 y383 y382 y381 KS0672 (top view) vss2 vdd2 test d10 d11 d12 d13 d14 d15 d00 d01 d02 d03 d04 d05 d20 d21 d22 d23 d24 d25 dio1 datpol vss1 clk2 vdd1 vgma2 vgma1 vgma3 vgma4 vgma5 vgma6 vgma7 vgma8 vgma10 vgma9 dio2 d40 d41 d42 d43 d44 d45 d30 d31 d32 d33 d34 d35 d50 d51 d52 d53 d54 d55 clk1 pol shl vdd2 vss2 vss2 vdd2 test d10 d11 d12 d13 d14 d15 d00 d01 d02 d03 d04 d05 d20 d21 d22 d23 d24 d25 dio1 datpol vss1 clk2 vdd1 vgma2 vgma1 vgma3 vgma4 vgma5 vgma6 vgma7 vgma8 vgma10 vgma9 dio2 d40 d41 d42 d43 d44 d45 d30 d31 d32 d33 d34 d35 d50 d51 d52 d53 d54 d55 clk1 pol shl vdd2 vss2 figure 2. KS0672 pin assignments
6 bit 384 channel tft-lcd source driver KS0672 7 pin descriptions symbol pin name description vdd1 logic power supply 2. 7 - 3.6 v vdd2 driver power supply 7 . 0 - 1 3 . 0 v vss1 logic ground ground (0 v) vss2 driver ground ground (0 v) y1 - y 384 driver outputs the d/a converted 6 4 gray scale analog voltage is output. d0<0: 5 > - d5<0: 5 > display data input the display data is input with a width of 36 bits, gray-scale data ( 6 bits) by 6 dots (r,g,b) dx0: lsb, dx 5 : msb shl shift direction control input this pin controls the direction of shift register in cascade connection. the shift direction of the shift registers is as follows. shl = h: dio1 input, y1 ? y 384 , dio2 output shl = l: dio2 input, y 384 ? y1, dio1 output dio1 start pulse input / output shl = h: used as the start pulse input pin. shl = l: used as the start pulse output pin. dio2 start pulse input / output shl = h: used as the start pulse output pin. shl = l: used as the start pulse input pin. datpol data inversion input datpol = l: display data is not inverted datpol = h: display data is inverted pol polarity input pol = h: the reference voltage for odd number outputs are vgma 1 ? vgma 5 and those for even number outputs are vgma 6 ? vgma 10 . pol = l: the reference voltage for odd number outputs are vgma 6 ? vgma 10 and those for even number outputs are vgma 1 ? vgma 5 . clk2 shift clock input refer to the shift register's shift clock input. the display data is loaded to the data register at the rising edge of clk2. clk1 latch input latches the contents of the data register at rising edge and transfers them to the d/a converter. also, after clk1 input, clears the internal shift register contents. after 1 pulse input on start, operates normally. clk1 input timing refers to the "relationships between clk1 start pulse (dio1, dio2) and blanking period" of the switching characteristic waveform. outputs the g/s data at falling edge. vgma1 ? vgma1 0 gamma corrected power supplies input the gamma corrected power supplies from external source. vdd2 > vgma1 > vgma2 > ??? > vgma 9 > vgma 10 > vss2 keep gray-scale power supply unchanged during the gray-scale voltage output. test test input test = l: normal operation mode test = h: test mode (op amp cut-off, rpd = 1 5 k w )
ks 0672 6 bit 384 channel tft-lcd source driver 8 operation description display data transfer when dio1 (or dio2) pulse is loaded into internal latch on the rising edge of clk2, dio1 (or dio2) pulse enables the operation of data transfer, so display data is valid on the next rising edge of clk2. once all the data of 384 channels are loaded into internal latch, it goes into stand-by state automatically, and any new data is not accepted even though clk2 is provided until next dio1 (or dio2) input. when next dio1 (or dio2) is provided, new display data is valid on the 2nd rising edge of clk2 after the rising edge of dio1 (or dio2). extension of output output pin can be adjusted to an extended screen by cascade connection. (1) shl = "l" connect dio1 pin of previous stage to the dio2 pin of next stage and all the input pins except dio1 and dio2 are connected together in each device. (2) shl = "h" connect dio2 pin of previous stage to the dio1 pin of next stage and all the input pins except dio2 and dio1 are connected together in each device. relationship between input data value and output voltage the lcd drive output voltages are determined by the input data and 10 (5 by 2) gamma corrected power supplies (vgma1 - vgma10). besides, to be able to deal with dot line inversion when mounted on a single- side, gradation voltages with different polarity can be output to the odd number output pins and the even number output pins. among 5-by-2 gamma corrected voltages, input gray-scale voltages of the same polarity with respect to the common voltage, for the respective 5 gamma corrected voltages of vgma1 - vgma5 and vgma6 - vgma10. shl = h last y1 y2 y3 y382 y383 y384 d00 - d05 d10 - d15 d20 - d25 d30 - d35 d40 - d45 d50 - d55 data first ...... ...... output first last - shl = l y1 y2 y3 y382 y383 y384 d00 - d05 d10 - d15 d20 - d25 d30 - d35 d40 - d45 d50 - d55 data ...... ...... output - figure 3. relationship between shift direction and output data
6 bit 384 channel tft-lcd source driver KS0672 9 vcom input data vgma1 vgma2 vgma3 vgma4 vgma5 vgma10 00h 08h 10h 18h 20h 28h 30h 38h 3fh vss2 vdd2 vgma9 vgma8 vgma6 vgma7 figure 4. gamma correction curve
ks 0672 6 bit 384 channel tft-lcd source driver 10 table 1. resistor strings (r0 - r62, unit: w w ) name value name value name value name value r0 500 r16 330 r32 175 r48 21 0 r1 500 r17 330 r33 175 r49 220 r2 500 r18 330 r34 1 70 r50 230 r3 500 r19 320 r35 1 70 r 51 24 0 r4 500 r20 300 r36 165 r52 250 r5 500 r21 280 r37 165 r53 260 r6 500 r22 270 r38 165 r54 27 0 r7 500 r23 260 r39 165 r55 290 r8 500 r24 250 r40 17 0 r56 300 r9 500 r25 240 r41 1 70 r57 310 r10 500 r26 230 r42 1 70 r58 320 r11 500 r27 220 r43 1 7 5 r59 340 r12 450 r28 210 r44 175 r60 340 r13 450 r29 200 r45 175 r61 340 r14 400 r30 190 r46 180 r62 340 r15 370 r31 180 r47 200
6 bit 384 channel tft-lcd source driver KS0672 11 table 2. relationship between input data and output voltage value input data dx5 dx4 dx3 dx2 dx1 dx0 g/s output voltage 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 00h 01h 02h 03 h 04h 05 h 06 h 07h 0 0 0 1 1 1 vh0 vh1 vh2 vh 3 vh4 vh 5 vh 6 vh7 vgma1 vgma1 + (vgma2 - vgma1) 500 / 7670 vgma1 + (vgma2 - vgma1) 1 0 00 / 7670 vgma1 + (vgma2 - vgma1) 1500 / 7670 vgma1 + (vgma2 - vgma1) 2000 / 7670 vgma1 + (vgma2 - vgma1) 2500 / 7670 vgma1 + (vgma2 - vgma1) 3000 / 7670 vgma1 + (vgma2 - vgma1) 3500 / 7670 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 1 0 08 h 09h 0a h 0b h 0ch 0d h 0e h 0fh 0 0 1 1 1 1 vh 8 vh9 vh 1 0 vh 1 1 vh12 vh 13 vh 1 4 vh15 vgma1 + (vgma2 - vgma1) 4000 / 7670 vgma1 + (vgma2 - vgma1) 4500 / 7670 vgma1 + (vgma2 - vgma1) 5000 / 7670 vgma1 + (vgma2 - vgma1) 5500 / 7670 vgma1 + (vgma2 - vgma1) 6000 / 7670 vgma1 + (vgma2 - vgma1) 6450 / 7670 vgma1 + (vgma2 - vgma1) 6900 / 7670 vgma1 + (vgma2 - vgma1) 7300 / 7670 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 10 h 11h 12 h 13 h 14h 15 h 16 h 17h 0 1 0 1 1 1 vh 16 vh17 vh 18 vh 19 vh20 vh2 1 vh2 2 vh23 vgma2 vgma2 + (vgma3 - vgma2) 330 / 4140 vgma2 + (vgma3 - vgma2) 660 / 4140 vgma2 + (vgma3 - vgma2) 990 / 4140 vgma2 + (vgma3 - vgma2) 1310 / 4140 vgma2 + (vgma3 - vgma2) 1610 / 4140 vgma2 + (vgma3 - vgma2) 1890 / 4140 vgma2 + (vgma3 - vgma2) 2160 / 4140 0 1 1 0 0 0 0 1 1 0 0 1 0 1 1 0 1 0 0 1 1 0 1 1 0 1 1 1 0 0 0 1 1 1 0 1 0 1 1 1 1 0 18 h 19h 1a h 1bh 1c h 1d h 1e h 1fh 0 1 1 1 1 1 vh24 vh25 vh2 6 vh27 vh2 8 vh2 9 vh 30 vh31 vgma2 + (vgma3 - vgma2) 2420 / 4140 vgma2 + (vgma3 - vgma2) 2670 / 4140 vgma2 + (vgma3 - vgma2) 2910 / 4140 vgma2 + (vgma3 - vgma2) 3140 / 4140 vgma2 + (vgma3 - vgma2) 3360 / 4140 vgma2 + (vgma3 - vgma2) 3570 / 4140 vgma2 + (vgma3 - vgma2) 3770 / 4140 vgma2 + (vgma3 - vgma2) 3960 / 4140 note: vdd2 > vgma1 > vgma2 > vgma3 > vgma4 > vgma5
ks 0672 6 bit 384 channel tft-lcd source driver 12 table 2. relationship between input data and output voltage value (continued) input data dx5 dx4 dx3 dx2 dx1 dx0 g/s output voltage 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 1 1 0 0 1 1 0 2 0h 21h 22h 23 h 24h 25 h 26 h 27h 1 0 0 1 1 1 vh 32 vh33 vh34 vh 35 vh36 vh 37 vh 38 vh39 vgma3 vgma3 + (vgma4 - vgma3) 175 / 2765 vgma3 + (vgma4 - vgma3) 350 / 2765 vgma3 + (vgma4 - vgma3) 520 / 2765 vgma3 + (vgma4 - vgma3) 690 / 2765 vgma3 + (vgma4 - vgma3) 855 / 2765 vgma3 + (vgma4 - vgma3) 1 020 / 2765 vgma3 + (vgma4 - vgma3) 1185 / 2765 1 0 1 0 0 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 1 0 1 1 0 1 1 1 0 28 h 29h 2a h 2b h 2ch 2d h 2e h 2fh 1 0 1 1 1 1 vh 40 vh41 vh 42 vh 43 vh44 vh 45 vh 46 vh47 vgma3 + (vgma4 - vgma3) 1350 / 2765 vgma3 + (vgma4 - vgma3) 1520 / 2765 vgma3 + (vgma4 - vgma3) 1690 / 2765 vgma3 + (vgma4 - vgma3) 1860 / 2765 vgma3 + (vgma4 - vgma3) 2035 / 2765 vgma3 + (vgma4 - vgma3) 2210 / 2765 vgma3 + (vgma4 - vgma3) 2385 / 2765 vgma3 + (vgma4 - vgma3) 2565 / 2765 1 1 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 0 1 1 0 0 1 1 1 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 1 0 30 h 31h 32 h 33 h 34h 35 h 36 h 37h 1 1 0 1 1 1 vh 48 vh49 vh 50 vh 51 vh52 vh53 vh54 vh55 vgma4 vgma4 + (vgma5 - vgma4) 210 / 4260 vgma4 + (vgma5 - vgma4) 430 / 4260 vgma4 + (vgma5 - vgma4) 660 / 4260 vgma4 + (vgma5 - vgma4) 900 / 4260 vgma4 + (vgma5 - vgma4) 1150 / 4260 vgma4 + (vgma5 - vgma4) 1410 / 4260 vgma4 + (vgma5 - vgma4) 1680 / 4260 1 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 38 h 39h 3a h 3bh 3c h 3d h 3e h 3fh 1 1 1 1 1 1 vh56 vh57 vh58 vh59 vh60 vh61 vh 62 vh63 vgma4 + (vgma5 - vgma4) 1970 / 4260 vgma4 + (vgma5 - vgma4) 2270 / 4260 vgma4 + (vgma5 - vgma4) 2580 / 4260 vgma4 + (vgma5 - vgma4) 2900 / 4260 vgma4 + (vgma5 - vgma4) 3240 / 4260 vgma4 + (vgma5 - vgma4) 3580 / 4260 vgma4 + (vgma5 - vgma4) 3920 / 4260 vgma5
6 bit 384 channel tft-lcd source driver KS0672 13 table 2. relationship between input data and output voltage value (continued) input data dx5 dx4 dx3 dx2 dx1 dx0 g/s output voltage 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 00h 01h 02h 03 h 04h 05 h 06 h 07h 0 0 0 1 1 1 vl0 vl1 vl2 vl 3 vl4 vl 5 vl 6 vl7 vgma1 0 vgma10 + (vgma9 - vgma10) 500 / 7670 vgma10 + (vgma9 - vgma10) 1000 / 7670 vgma10 + (vgma9 - vgma10) 1500 / 7670 vgma10 + (vgma9 - vgma10) 2000 / 7670 vgma10 + (vgma9 - vgma10) 2500 / 7670 vgma10 + (vgma9 - vgma10) 3000 / 7670 vgma10 + (vgma9 - vgma10) 3500 / 7670 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 1 0 08 h 09h 0a h 0b h 0ch 0d h 0e h 0fh 0 0 1 1 1 1 vl 8 vl9 vl 1 0 vl 1 1 vl12 vl 13 vl 1 4 vl15 vgma10 + (vgma9 - vgma10) 4000 / 7670 vgma10 + (vgma9 - vgma10) 4500 / 7670 vgma10 + (vgma9 - vgma10) 5000 / 7670 vgma10 + (vgma9 - vgma10) 5500 / 7670 vgma10 + (vgma9 - vgma10) 6000 / 7670 vgma10 + (vgma9 - vgma10) 6450 / 7670 vgma10 + (vgma9 - vgma10) 6900 / 7670 vgma10 + (vgma9 - vgma10) 7300 / 7670 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 10 h 11h 12 h 13 h 14h 15 h 16 h 17h 0 1 0 1 1 1 vl 16 vl17 vl 18 vl 19 vl20 vl2 1 vl2 2 vl23 vgma9 vgma9 + (vgma8 - vgma9) 330 / 4140 vgma9 + (vgma8 - vgma9) 660 / 4140 vgma9 + (vgma8 - vgma9) 990 / 4140 vgma9 + (vgma8 - vgma9) 1310 / 4140 vgma9 + (vgma8 - vgma9) 1610 / 4140 vgma9 + (vgma8 - vgma9) 1890 / 4140 vgma9 + (vgma8 - vgma9) 2160 / 4140 0 1 1 0 0 0 0 1 1 0 0 1 0 1 1 0 1 0 0 1 1 0 1 1 0 1 1 1 0 0 0 1 1 1 0 1 0 1 1 1 1 0 18 h 19h 1a h 1bh 1c h 1d h 1e h 1fh 0 1 1 1 1 1 vl24 vl25 vl2 6 vl27 vl2 8 vl2 9 vl 30 vl31 vgma9 + (vgma8 - vgma9) 2420 / 4140 vgma9 + (vgma8 - vgma9) 2670 / 4140 vgma9 + (vgma8 - vgma9) 2910 / 4140 vgma9 + (vgma8 - vgma9) 3140 / 4140 vgma9 + (vgma8 - vgma9) 3360 / 4140 vgma9 + (vgma8 - vgma9) 3570 / 4140 vgma9 + (vgma8 - vgma9) 3770 / 4140 vgma9 + (vgma8 - vgma9) 3960 / 4140 note: vgma6 > vgma7 > vgma8 > vgma9 > vgma10 > vss2
ks 0672 6 bit 384 channel tft-lcd source driver 14 table 2. relationship between input data and output voltage value (continued) input data dx5 dx4 dx3 dx2 dx1 dx0 g/s output voltage 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 1 1 0 0 1 1 0 2 0h 21h 22h 23 h 24h 25 h 26 h 27h 1 0 0 1 1 1 vl 32 vl33 vl34 vl 35 vl36 vl 37 vl 38 vl39 vgma 8 vgma8 + (vgma7 - vgma8) 175 / 2765 vgma8 + (vgma7 - vgma8) 350 / 2765 vgma8 + (vgma7 - vgma8) 520 / 2765 vgma8 + (vgma7 - vgma8) 690 / 2765 vgma8 + (vgma7 - vgma8) 855 / 2765 vgma8 + (vgma7 - vgma8) 1020 / 2765 vgma8 + (vgma7 - vgma8) 1185 / 2765 1 0 1 0 0 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 1 0 1 1 0 1 1 1 0 28 h 29h 2a h 2b h 2ch 2d h 2e h 2fh 1 0 1 1 1 1 vl 40 vl41 vl 42 vl 43 vl44 vl 45 vl 46 vl47 vgma8 + (vgma7 - vgma8) 1350 / 2765 vgma8 + (vgma7 - vgma8) 1520 / 2765 vgma8 + (vgma7 - vgma8) 1690 / 2765 vgma8 + (vgma7 - vgma8) 1860 / 2765 vgma8 + (vgma7 - vgma8) 2035 / 2765 vgma8 + (vgma7 - vgma8) 2210 / 2765 vgma8 + (vgma7 - vgma8) 2385 / 2765 vgma8 + (vgma7 - vgma8) 2565 / 2765 1 1 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 0 1 1 0 0 1 1 1 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 1 0 30 h 31h 32 h 33 h 34h 35 h 36 h 37h 1 1 0 1 1 1 vl 48 vl49 vl 50 vl 51 vl52 vl53 vl54 vl55 vgma7 vgma7 + (vgma6 - vgma7) 210 / 4260 vgma7 + (vgma6 - vgma7) 430 / 4260 vgma7 + (vgma6 - vgma7) 660 / 4260 vgma7 + (vgma6 - vgma7) 900 / 4260 vgma7 + (vgma6 - vgma7) 1150 / 4260 vgma7 + (vgma6 - vgma7) 1410 / 4260 vgma7 + (vgma6 - vgma7) 1680 / 4260 1 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 38 h 39h 3a h 3bh 3c h 3d h 3e h 3fh 1 1 1 1 1 1 vl56 vl57 vl58 vl59 vl60 vl61 vl 62 vl63 vgma7 + (vgma6 - vgma7) 1970 / 4260 vgma7 + (vgma6 - vgma7) 2270 / 4260 vgma7 + (vgma6 - vgma7) 2580 / 4260 vgma7 + (vgma6 - vgma7) 2900 / 4260 vgma7 + (vgma6 - vgma7) 3240 / 4260 vgma7 + (vgma6 - vgma7) 3580 / 4260 vgma7 + (vgma6 - vgma7) 3920 / 4260 vgma6
6 bit 384 channel tft-lcd source driver KS0672 15 absolute maximum ratings t able 3. absolute maximum ratings (vss1 = vss2 = 0 v) parameter symbol ratings unit logic supply voltage vdd1 -0.3 to 5. 5 v driver supply voltage vdd2 -0.3 to 1 5.0 v vgma1 - 5 0.4 vdd2 to vdd2 + 0.3 vgma6 - 10 -0.3 to 0.6 vdd2 input voltage others -0.3 to vdd1 + 0.3 v dio1, 2 -0.3 to vdd1 + 0.3 output voltage y1 - y 384 -0.3 to vdd2 + 0.3 v operating power dissipation pd 2 00 mw operation temperature top -20 to 75 c storage temperature tstg -55 to 1 25 c cautions: if lsis are stressed beyond those listed above ? absolute maximum ratings ? , they may be permanently destroyed. these are stress ratings only, and functional operation of the device at these or any other condition beyond those indicated under ? recommended operating conditions ? is not implied. exposure to absolute maximum rated conditions for extended periods may affect device reliability. turn on power order: vdd1 ? control signal input ? vdd2 ? vgma1 - vgma10 turn off power order: vgma1 - vgma10 ? vdd2 ? control signal input ? vdd1 recommended operation condition s table 4. recommended operation conditions ( ta = -20 to 75 c , vss1 = vss2 = 0 v) parameter symbol min. typ. max. unit logic supply voltage vdd1 2.7 3.0 3.6 v driver supply voltage vdd2 7 . 0 9 .0 1 3 . 0 v vgma1 - vgma 5 0.5 vdd2 - vdd2 - 0. 2 v gamma corrected voltage vgma 6 - vgma1 0 vss2 + 0. 2 - 0.5 vdd2 v driver part output voltage vyo vss2 + 0. 2 - vdd2 - 0. 2 v maximum clock frequency fmax vdd1 = 2.7 v 65 mhz output load capacitance cl - - 200 pf / pin
ks 0672 6 bit 384 channel tft-lcd source driver 16 dc characteristics table 5. dc characteristics ( ta = -20 to 75 c, vdd1 = 2. 7 to 3.6 v, vdd2 = 7 to 1 3 v, vss1 = vss2 = 0 v ) parameter symbol condition min. typ. max. unit high level input voltage vih 0.7 vdd1 - vdd1 low level input voltage vil 0 - 0. 3 vdd1 v input leakage current il shl, clk2, d00 - d5 5 , clk1, pol, datpol, dio1 (dio2) -1 - 1 m a high level output voltage voh dio1 (dio2), io = -1.0 ma vdd1 - 0.5 - - low level output voltage vol dio1 (dio2), io = +1.0 ma - - 0.5 v resistor r0 - r 62 refer to table 1. resistor strings rn 0.7 rn 1.3 w ivoh vdd2 = 9 .0 v, vx = 2 .5 v, vyo = 8 .5 v - -0.5 -0.3 ma driver output current ivol vdd2 = 9 .0 v, vx = 6.5 v, vyo = 0.5 v 0.3 0.5 - ma vss2 + 0. 2 v to vdd2 - 1.5 v - 10 20 output voltage deviation d vo vdd2 - 1.5 v to vdd2 - 0. 2 v - 1 5 2 5 output rms voltage deviation dvrms (2) input data: 00h to 3 fh - 5 1 5 mv output voltage range vyo input data: 00h to 3 fh vss2 + 0.2 - vdd2 - 0. 2 v logic part dynamic current idd1 vdd1 = 3.0 v (3) - 4.0 5.5 driver part dynamic current idd2 vdd 1 = 3.0 v, vdd2 = 9.0 v , vgma1 = 8.5 v, vgma5 = 5.0 v, vgma6 = 4.0 v, vgma10 = 0.5 v (3 ) (4 ) (5) - 4 .0 7 .0 ma notes: 1. vyo is the output voltage of analog output pins y1 to y384. vx is the voltage applied to analog output pins y1 to y384. 2. dvrms is a maximum deviation value from ideal difference between high output and low output at the same gray scale. 3. clk1 period is defined to be 20 m s at fclk2 = 33 mhz, data pattern = 101010 , (checkerboard pattern), ta = 25 c 4. the current consumption per driver when xga single-sided mounting (8 drivers) is connected in cascade 5. no load
6 bit 384 channel tft-lcd source driver KS0672 17 ac characteristics table 6. ac characteristics ( ta = -20 to 75 c, v dd2 = 7 to 13 v, vdd1 = 2.7 to 3.6 v, v ss1 = vss2 = 0 v) p arameter s ymbol c ondition min. typ. m ax . u nit clock pulse width pwclk - 1 5 - - clock pulse low period pwclk(l) - 5 - - clock pulse high period pwclk(h) - 5 - - data setup time tsetup1 (1) 3 / 5 - - data hold time thold1 (1) 0 / 2 - - start pulse setup time tsetup2 (1) 3 / 5 - - start pulse hold time thold2 (1) 0 / 2 - - datpol-clk2 setup time tsetup4 (1) 3 / 5 - - datpol-clk2 hold time thold4 (1) 0 / 2 0 - start pulse delay time tplh1 cl = 20 pf - - 1 2 ns clk1 setup time tsetup3 - 1 - - clk2 period driver output delay time1 tphl1 (2),(4) - - 5 driver output delay time2 tphl2 (3),(4) - - 10 clk1 pulse high period pwclk1 - 0. 2 - 2 m s data invalid period tinv dio1 (2) - ? clk2 - 1 last data timing tldt - 1 - - clk2 period clk1-clk2 time tclk1 ? clk2 clk1 - ? clk2 - 6 - - ns pol-clk1 time tpol ? clk1 pol - or ? clk1 - 5 - - ns notes: 1. input condition (vih = 0.7 vdd1, vil = 0.3 vdd1 / vih = 0.5 vdd1, vil = 0.5 vdd1) 2. the value is specified when the drive voltage value reaches the target output voltage level of 90% 3. the value is specified when the drive voltage value reaches the target output voltage level of 6-bit accuracy. 4. yout load condition vcom = 0.5vdd2 10k w 20k w 20k w 30pf 30pf 30pf yout figure 5. yout load condition
ks 0672 6 bit 384 channel tft-lcd source driver 18 waveforms clk2 tldt 0.5vdd1 invalid data last data clk1 dxx tclk1-clk2 tsetup1 pwclk(h) invalid data clk2 dio1 input (dio2 input) clk1 y(1:384) 1st last-1 last pwclk(l) vih vil thold1 tplh1 target output voltage 90% target output voltage dxx datpol1 datpol2 pwclk tsetup2 1st data tsetup4 thold2 thold4 dio2 output (dio1 output) tsetup3 hi-z pwclk1 tphl2 tinv tphl1 pol tpol-clk1 figure 6. waveforms
6 bit 384 channel tft-lcd source driver KS0672 19 relationships between clk1, start pulse (dio1, dio2) and blanking period tldt invalid data clk2 dio1 input (dio2 input) clk1 dxx 1st data 1clk2(min.) nth data n-1th data 2nd data blanking time = min. 3clk2 last data first data in the next line 0.5vdd1 1clk2 hi-z vgma6 - vgma10 vgma1 - vgma5 clk1 pol y 2n-1 :odd number output y 2n :even number output vgma1 - vgma5 vgma1 - vgma5 vgma6 - vgma10 hi-z hi-z hi-z vgma6 - vgma10 figure 7. waveforms

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